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     EduGorilla 
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    FET voltage divider bias circuit is shown in the given figure. If ID = 4 mA, V GS and VDS will be, respectively

    Options :-

    1. –3.78 V and 4 V
    2. 4 V and –3.78 V
    3. –3.78 V and –4 V
    4. –4 V and –3.78 V
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Reply To: FET voltage divider bias circuit is shown in the given figure. If ID = 4 mA, V GS and VDS will be, r….
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