- 07/12/2019 at 10:31 pm #1428174EduGorillaKeymasterSelect Question Language :
Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is _____.
Options :-Post your Training /Course EnquiryAre You looking institutes / coaching center for
- IIT-JEE, NEET, CAT
- Bank PO, SSC, Railways
- Study Abroad