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     EduGorilla 
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    Consider a system in which bus cycle takes 100 ns. Transfer of bus control from processor to device or device to processor, takes 250 ns. One of the IO device has data transfer rate of 100 KB/sec and employs DMA. Data are transferred one byte at a time.

    Suppose we employ DMA in a burst mode. That is, the DMA interface gains bus mastership prior to the start of block transfer and maintains control of the bus until the whole block is transferred. How long would the device tie up with the bus when transferring a block of 256 bytes ___________

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