- 07/13/2019 at 1:42 pm #1434493EduGorillaKeymasterSelect Question Language :
Consider a 5-bit right shift register each shifting data to the right for every clock pulse. The serial input A is derived by using NAND gates as shown in figure. If the initial content of the counter is 10001 at Q0Q1Q2Q3Q4 by applying the clock signal then after how many clock pulse circuit is back to the initial state?
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